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Apple Silicon How XNU adapts to Apple-designed chips: APRR/SPRR for fast W↔X switching, unified memory, the AMX matrix coprocessor, and Rosetta 2's x86_64 translation.
Apple Silicon SoC layout High-level SoC layout shared by every M-series chip: a performance-core cluster and an efficiency-core cluster (each with its own L2 cache and AMX coprocessor), a GPU, the Secure Enclave, all sitting on a unified-memory fabric. Apple Silicon SoC die · single package · unified memory architecture Performance cluster P-cores · wide pipeline P-core 0 P-core 1 P-core 2 P-core 3 L2 shared across cluster · AMX coprocessor Efficiency cluster E-cores · low power E-core 0 E-core 1 E-core 2 E-core 3 L2 shared across cluster · own AMX GPU N cores Metal Tile-based deferred rendering Neural Engine ANE · 16 cores Media engines ProRes · H.264 · HEVC Display engine Secure Enclave (SEP) own ARM core · own RAM · SEPOS AIC Apple Interrupt Controller · per-cluster routing pmgr · DVFS · power islands cluster-level voltage / frequency scaling UNIFIED MEMORY FABRIC · ~400 GB/s · single physical address space CPU clusters, GPU, ANE, media engines, SEP all map the same DRAM DRAM modules (in-package) LPDDR5 · 8 / 16 / 32 / 64 / 128 / 192 GB Heterogeneous: scheduler picks P vs E per thread via QoS recommendation. Unified memory: zero-copy GPU↔CPU. Apple Silicon: structure at a glance.