Skip to content

Subsystem · The hardware tier

Apple Silicon

How XNU adapts to Apple-designed chips: APRR/SPRR for fast W↔X switching, unified memory, the AMX matrix coprocessor, and Rosetta 2's x86_64 translation.

apple-oss-distributions/xnuosfmk/arm64/start.sStart reading the kernel source here.View on GitHub(line —)
Apple Silicon SoC layoutHigh-level SoC layout shared by every M-series chip: a performance-core cluster and an efficiency-core cluster (each with its own L2 cache and AMX coprocessor), a GPU, the Secure Enclave, all sitting on a unified-memory fabric.Apple Silicon SoCdie · single package · unified memory architecturePerformance clusterP-cores · wide pipelineP-core 0P-core 1P-core 2P-core 3L2 shared across cluster · AMX coprocessorEfficiency clusterE-cores · low powerE-core 0E-core 1E-core 2E-core 3L2 shared across cluster · own AMXGPUN coresMetalTile-baseddeferred renderingNeural EngineANE · 16 coresMedia enginesProRes · H.264 · HEVCDisplay engineSecure Enclave (SEP)own ARM core · own RAM · SEPOSAICApple Interrupt Controller · per-cluster routingpmgr · DVFS · power islandscluster-level voltage / frequency scalingUNIFIED MEMORY FABRIC · ~400 GB/s · single physical address spaceCPU clusters, GPU, ANE, media engines, SEP all map the same DRAMDRAM modules (in-package)LPDDR5 · 8 / 16 / 32 / 64 / 128 / 192 GBHeterogeneous: scheduler picks P vs E per thread via QoS recommendation. Unified memory: zero-copy GPU↔CPU.
Apple Silicon: structure at a glance.

Articles in this series

Apple Silicon and XNU: APRR, unified memory, AMX, Rosetta 2
What changed in XNU when Apple shipped its own ARM silicon — P/E cores, APRR page-permission switching, the AMX matrix coprocessor, and Rosetta 2.
apple-siliconarm64rosettaamx
Page tables on Apple Silicon: ASIDs, translation regimes, and APRR in detail
How XNU maps virtual to physical on Apple Silicon — the ARM translation regime, multi-level page tables, ASIDs that eliminate TLB flushes, and where APRR sits in the translation pipeline.
apple-siliconarm64pmapasid
The Apple GPU and Metal driver: unified memory in practice
How macOS's GPU driver hands off work to Apple Silicon's tile-based deferred renderer, and why unified memory makes IOSurface zero-copy across CPU and GPU.
apple-silicongpumetaliokit
AOP and the secondary coprocessors on Apple Silicon
The Apple SoC isn't just CPU + GPU + SEP. AOP, ANE, ISP, AMC, AMX — half a dozen secondary processors that quietly handle sensors, ML, imaging, and accelerated workloads.
apple-siliconaopaneisp
Boot ROM and Secure Boot on Apple Silicon: from power-on to iBoot
What runs in the first microseconds of a Mac boot — the SoC's Boot ROM, the Apple-signed LLB and iBoot stages, the SEP coming up alongside, and how the chain of trust starts.
apple-siliconbootsecure-bootiboot
Power management on Apple Silicon: pmgr, DVFS, and idle clusters
How macOS keeps an Apple Silicon Mac running for 18 hours on a battery — cluster-level voltage scaling, idle gating, the pmgr driver, and the power-island architecture.
apple-siliconpowerpmgrdvfs
The Apple GPU command pipeline: Metal to silicon
From a MTLCommandBuffer.commit call to the shader cores running — the userspace encoder, the kernel driver's IOConnectCallMethod, the GPU firmware processor, and where commands actually dispatch.
apple-silicongpumetaliokit