Skip to content
Back to the map

Map · The hardware tier

Apple Silicon

How XNU adapts to Apple-designed chips: APRR/SPRR for fast W↔X switching, unified memory, the AMX matrix coprocessor, and Rosetta 2's x86_64 translation.

apple-oss-distributions/xnuosfmk/arm64/start.sStart reading the kernel source here.View on GitHub(line —)
Apple Silicon SoC layoutHigh-level SoC layout shared by every M-series chip: a performance-core cluster and an efficiency-core cluster (each with its own L2 cache and AMX coprocessor), a GPU, the Secure Enclave, all sitting on a unified-memory fabric.Apple Silicon SoCdie · single package · unified memory architecturePerformance clusterP-cores · wide pipelineP-core 0P-core 1P-core 2P-core 3L2 shared across cluster · AMX coprocessorEfficiency clusterE-cores · low powerE-core 0E-core 1E-core 2E-core 3L2 shared across cluster · own AMXGPUN coresMetalTile-baseddeferred renderingNeural EngineANE · 16 coresMedia enginesProRes · H.264 · HEVCDisplay engineSecure Enclave (SEP)own ARM core · own RAM · SEPOSAICApple Interrupt Controller · per-cluster routingpmgr · DVFS · power islandscluster-level voltage / frequency scalingUNIFIED MEMORY FABRIC · ~400 GB/s · single physical address spaceCPU clusters, GPU, ANE, media engines, SEP all map the same DRAMDRAM modules (in-package)LPDDR5 · 8 / 16 / 32 / 64 / 128 / 192 GBHeterogeneous: scheduler picks P vs E per thread via QoS recommendation. Unified memory: zero-copy GPU↔CPU.